1. Field of the Invention
The present invention relates to a vertical power MOS transistor which is capable of preventing a short circuit between gate and source electrodes in the gate electrode edge portion.
2. Description of the Background Art
In FIG. 1, there is shown a conventional power MOS transistor, as disclosed in "Field-Effect and Bipolar Power Transistor Physics", written by Blicher, published by Academic Press, 1981, pp. 280 to 282.
In FIG. 1, an n.sup.- -type drain region 7 is formed on a high concentration n.sup.+ -type substrate 8, and p-type channel regions 2 are formed in the upper surface area of the drain region 7. A pair of n.sup.+ -type source regions 1 are formed in the right and left portions of the upper surface area of each channel region 2 and a high concentration p.sup.+ -type region 10 is formed in the upper surface area of the channel region 2 between the source regions 1. An insulating gate oxide film 3 is formed on the surface of the drain region 7 so as to connect the two source regions 1 of the two adjacent channel regions 2, and a gate electrode 4 is formed on the greater portion of the gate oxide film 3 to bridge over the partial areas of the two source regions 1, the two adjacent channel regions 2 and the drain region 7 therebetween through the gate oxide film 3. The gate electrode 4 is completely covered by the insulating film 5 formed on the gate oxide film 3. A source electrode 6 is formed on the entire upper surface of thus the obtained substrate, and thus the source electrode 6 directly contacts the source regions 1 and also contacts the channel regions 2 via the high concentration p.sup.+ -type regions 10. A drain electrode 9 is attached to the lower surface of the high concentration n.sup.+ -type substrate 8.
In the vertical power MOS transistor, several thousands to several tens of thousands of cells having the construction described above are connected in parallel.
There is shown in FIG. 2 one cell unit of the vertical power MOS transistor described above. The insulating film 5 is usually obtained by forming a PSG film, which is comprised of a SiO.sub.2 film in which phosphor is doped in a high concentration, using the CVD method. However, the PSG film 5 sometimes fails to entirely cover the gate electrode 4, which is usually made of a polycrystalline silicon, resulting in a step coverage failure, i.e., a short circuit portion 100 between the source and gate electrodes 6 and 4 in the gate electrode edge portion.
In such a case, even when the step coverage failure happens, i.e., the PSG film 5 does not cover the entire of the gate electrode 4 in one cell unit, since the source electrode 6 completely covers the upper surface of the trasistor, the short circuit is caused between the source and gate electrodes 6 and 4. That is, the step coverage failure in one cell unit brings about the failure of the whole of the integrated vertical power MOS transistor including several thousands to several tens of thousands of cell units connected in parallel to one another.
In order to prevent this problem, various measures have been proposed. For instance, after the deposition of the PSG film on the gate electrode, the PSG film is reflowed in order to remove the step coverage failure. In this method, since a heat treatment at a high temperature is required, the source regions 1 previously formed are deeply diffused, and this method can not be properly applied to minute processing.
When the phosphor concentration in the PSG film is raised, reflowing can be carried out at a low temperature. However, in this method, the water absorption of the PSG film is extremely increased, and hence the phosphor contained in the PSG film readily changes to phosphoric acid. Accordingly, the corrosion of the aluminum source electrode takes place.
By forming the PSG film thickly it is possible to improve the step coverage failure. However, cracks are likely with a thick PSG film, and further it is difficult to perform the minute processing of contact portions.